Abstract: Supporting QoS in IP networks has been a research hotspot in recent years, and the new storage device launched by IDT, Multi-Queue FIFO, can support QoS applications. Because it supports multiple queues that can be configured under a single device, and has a high degree of flexibility for cascading use, the device has a good application prospect in supporting data distinguishing cache and processing. The main characteristics of the multi-queue FIFO are introduced, and the FPGA control method and its application to support QoS scheduling in routers are given.
To support QoS (Quality of Service) in IP networks, in addition to the development and improvement of related network protocols, it is also necessary to provide differentiated services for different types of packets or data streams within the router. Multi-queue FIFO is a new type of storage device first launched by IDT in 2002, which can effectively support the high-speed implementation of QoS. The chip is designed to improve network service quality and other applications that require reordering of queue data. It not only supports flexible data differentiation applications, but also avoids complex off-chip control logic. This article introduces the basic characteristics of the device and the FPGA control method, and gives the application of the memory to support QoS scheduling in the router. 
1 Introduction to Multi-Queue FIFO
The device is equipped with an embedded FIFO memory core and high-speed queue logic, with high data transmission bandwidth and flexible configurability. The device single chip supports a maximum continuous transmission rate of 7.2Gbps and supports up to 32 sub-queues, and the device cascade supports up to 256 sub-queues. Only one FIFO can buffer multiple data streams, which helps users select different queues to perform independent read and write functions.
The multi-queue FIFO not only provides traditional FIFO functions such as data buffering, queue full and empty status indication, write / read clock independence and write / read bus matching, but also supports the entire packet operation mode (Packet Mode) and data queuing, thereby eliminating Previously, expensive and complicated operation logic was used to achieve similar functions. The schematic diagram of multi-queue FIFO is shown in Figure 1.
It can be seen intuitively from the figure that the multi-queue FIFO is a memory that provides distinguishable multiple logical sub-queues within a physical device. Differentiable means that each sub-queue can be independently written / read, and each sub-queue has an independent status indication. 
2 FPGA control of multi-queue FIFO
FPGA control of multi-queue FIFO is reflected in three aspects: configuration, write operation and read operation, as shown in Figure 2.
2.1 Configuration of multi-queue FIFO
The new IDT multi-queue flow control device provides system designers with the latest solution that enables multiple selectable sequential data access operations with only one highly integrated device. This flexible function can be realized by a series of device setting options. Unlike previous single-queue FIFO devices (such as IDT 3690), multi-queue FIFOs have relatively complex configurability. In addition to the write / read port bus width that can be directly set by chip pins, there are two corresponding configurations Method: default configuration and serial configuration, where serial configuration is also called user-defined configuration, which is a new device feature.
image 3
The configurable items of the multi-queue FIFO are: (a) the number of logical sub-queues in the device; (b) the storage depth of each sub-queue; (c) the PAF (almost full) offset value of each sub-queue; (d) each sub-queue The queue's PAE (almost empty) offset value (valid in normal mode and changed to full packet indication PR in full packet mode).
The user has great flexibility in the configuration of the multi-queue FIFO. For example, IDT72V51336 ~ IDT72V51356 can be configured into 1 to 8 queues, and the depth setting of each queue is independent of each other. The flag is user programmable and each sub-queue is independent. Configuration can be done through a dedicated serial programming port. If you do not need to program the device, you can use the default mode. 
Serial configuration means that the data of the multi-queue FIFO is serially sent to the device bit by bit. Inside the multi-queue FIFO device, there are registers that store configuration data. These registers take 18 bits as a basic unit. Let Q be the number of sub-queues configured by the device and Qmax be the maximum number of sub-queues supported by the device. There are (Qmax & TImes; 4 + 1) registers in the device. The amount of bit data Sum required for a single device configuration is: 18 + Qx72 + 1. The last bit is the end-of-configuration indication. If Q = 8 in the design, Sum = 19 + 8x72 = 595 bits. The specific setting basis of the configuration data can be found in IDT document AN-303 (DSC-5997 / 2, July 2003 version).
The serial configuration signal timing (single device) is shown in Figure 3.
If multiple devices are used in cascade, the SO and SENO ~ of device i should be connected to the SI and SENI ~ of device i + l, respectively, and the SENO ~ of the cascade tail device should be detected to judge whether the entire configuration is finished. When writing a serial configuration program in a hardware description language, you should refer to the serial configuration flow state diagram shown in Figure 4.
The "configuration data" in the figure can be stored either in the on-chip RAM of the FPGA or in the off-chip memory. Due to the small amount of configuration data, it is recommended to choose to store in on-chip RAM, because it can save the interconnection with off-chip memory.
2.2 Write operation
The multi-queue FIFO is used to distinguish each write / read sub-queue from the queue address Wradd / Rdadd. The high level of the lock valid signal Waden / Raden is used to specify a new write / read sub-queue. The write / read enable is Wen / Ren.
Multi-queue FIFO write operation has a delay effect compared to the switch of write queue address, that is, the data on the write bus is sent to the new sub-queue in the second write clock cycle after the new sub-queue address is locked. If you can use this timing feature to lock the new sub-queue address two cycles in advance, you can use 100% write bus cycles.
When the sub-queue full indication FF is valid, new data cannot be written to the queue, and data loss will occur. Generally, in order to avoid this situation, the PAF offset value must be configured. After seeing that PAFn ~ is pulled low, the write operation is stopped. Figure 5 shows the timing diagram of the uninterrupted write operation.
Figure 5
2.3 Read operation
The read operation similar to the write operation also has a delay effect relative to the read queue address, that is, in the third read clock cycle after the new queue address is locked, the data presented on the read bus changes to the data in the new sub-queue. So if you can lock the new queue three cycles in advance, you can achieve 100% read bus utilization.
When the status of the selected queue is empty, the read port shows a full high level. After configuring the PAE offset value, you can know the empty or non-empty status of the queue by looking at PAEn ~, and read or switch the new queue in advance. Figure 6 shows the timing diagram of the uninterrupted read operation.
Image 6
3 Application of multi-queue FIFO
Multi-queue FIFO can meet the requirements of equipment to achieve quality of service, packet priority and multiple data stream aggregation / separation. For example, according to the customized priority order of the packet customers, the data entering the system can be distributed to one of multiple queues, each of which represents a different service level. The processor first processes high-priority packets according to a certain algorithm to ensure the service level of the entire network. The author used multi-queue FIFO to implement multi-priority scheduling in the backbone router switching network. The specific example is shown in Figure 7.
The classification of service levels is usually based on the type of packet, and high priority is given to delay-sensitive packets. Different from traditional first-come-first-served (FCFS), differentiated services can provide a certain quality of network service. Figure 8 is a specific example. If you do not use multi-queue FIFO, it is necessary to use SRAM to simulate multi-queue, and you have to add a lot of complex control logic and consume processor resources; PCB manufacturing is difficult and has poor scalability. 
In addition, in the case of continuous operation of continuous power, FPGA can control the configuration of the multi-queue FIFO at different times to adapt to different application needs. For example, to adapt to different types of data, it can be serially configured into corresponding multiple sub-queues during temporary storage; while only doing the same type of data buffer can sometimes be configured as a single queue. Therefore, the multi-queue FIFO application has high flexibility and good prospects.
The pin refers to the connection between the internal circuit of the integrated circuit (chip) and the peripheral circuit, and the pin constitutes the interface of the chip. According to the function, the pins of AT89S52 can be divided into four categories: main power supply, external crystal oscillator or oscillator, multi-function I/O port, and control, strobe and reset.
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