Analysis of 30 wrong ideas and causes in hardware design:
One: cost savings
Phenomenon 1: The resistance of these pull-up/pull-down resistors is not big, so choose an integer 5K.
Comments: There is no 5K resistance value on the market, the closest is 4.99K (accuracy 1%), followed by 5.1K (accuracy 5%), and its cost is 4 times and 2 times higher than the 4.7K with 20% accuracy. . The resistance of 20% precision is only 1, 1.5, 2.2, 3.3, 4.7, 6.8 (including integer multiples of 10); similarly, 20% precision capacitors only have the above values, if other ones are selected Values ​​must use higher precision, and the cost can be multiplied several times without any benefit.
Phenomenon 2: What color is the indicator on the panel? I think blue is special, just choose it.
Comments: Other colors, such as red, green, yellow and orange, regardless of size (5MM or less), have matured for decades, the price is generally less than 5 cents, and blue is something that was invented in the last three or four years. Both technical maturity and supply stability are poor, and prices are four or five times more expensive. At present, the blue indicator light is only used when it cannot be replaced by other colors, such as displaying a video signal.
Phenomenon 3: This logic can also be used with the 74XX gate circuit, but it is too earthy, or use CPLD, it looks more upscale.
Comments: 74XX's door circuit is only a few cents, and CPLD has at least dozens of pieces (GAL/PAL is only a few dollars, but the company does not recommend it). The cost has been increased by N times, and the work of production, documentation, etc. has been added several times.
Phenomenon 4: Our system requirements are so high, including MEM, CPU, FPGA, etc. All chips must be selected the fastest.
Comment: Not all parts of a high-speed system work at high speeds, and for every level of device speed, the price is almost doubled, and it also has a significant negative impact on signal integrity issues.
Phenomenon 5: The PCB design requirements of this board are not high, just use a thin line and automatically cloth it.
Comments: Automated wiring must occupy a larger PCB area, and at the same time produce more than a lot of vias than manual wiring. In large batches of products, the factors considered by PCB manufacturers to cut prices are line width and The number of holes, which affect the yield of the PCB and the consumption of the drill bit, respectively, saves the cost of the supplier, and finds a reason for the price reduction.
Phenomenon 6: As long as the program is stable, the code is longer, and the efficiency is not critical.
Comments: CPU speed and memory space are bought with money. If you spend a few days to improve the efficiency of the program when writing code, then the cost saved by reducing the CPU frequency and reducing the memory capacity is definitely cost-effective. The CPLD/FPGA design is similar.
Two: low power design
Phenomenon 1: Our system is 220V power supply, so we don't care about power consumption.
Comments: Low-power design is not just to save power. More benefits are reduced cost of power modules and cooling systems, and reduced electromagnetic radiation and thermal noise due to reduced current. As the temperature of the device decreases, the device life is extended accordingly (for every 10 degrees increase in the operating temperature of the semiconductor device, the lifetime is reduced by half)
Phenomenon 2: These bus signals are pulled with resistance, feel relieved
Comments: There are many reasons why the signal needs to be pulled up, but not all of them have to be pulled. The pull-down resistor pulls a simple input signal, and the current is tens of microamps or less. However, if a signal is driven, the current will reach milliamperes. The current system is usually 32 bits of address data, and there may be After the 244/245 isolated bus and other signals are pulled up, the power consumption of a few watts is consumed by these resistors (do not use the concept of 8 cents per kilowatt to treat the power consumption of these watts).
Phenomenon 3: How to deal with these unused I/O ports of CPU and FPGA? Let it be empty, let's talk later.
Comments: If the unused I/O port is left floating, it may become an input signal of repeated oscillations due to a little interference from the outside world, and the power consumption of the MOS device basically depends on the number of times the gate circuit is flipped. If you pull it up, each pin will also have a micro-ampere current, so the best way is to set it as an output (of course, you can't connect other driven signals outside)
Phenomenon 4: There are so many doors left in this FPGA, so let's play it out.
Comments: The power consumption of FGPA is proportional to the number of flip-flops used and the number of flips, so the power consumption of the same model FPGA at different times of different circuits may differ by a factor of 100. Minimizing the number of flip-flops at high speeds is the fundamental way to reduce FPGA power consumption.
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