The sensor network represents the convergence of information acquisition (sensing), data transmission, and signal processing technologies. In certain scenarios, communication cannot depend on pre-established infrastructure; instead, it requires a mobile communication system capable of dynamically forming a temporary network. As a result, sensor networks are gradually ushering humanity into an era where "network" and "sensor" become the core of daily life.
At the heart of any RF receiver is the low noise amplifier (LNA), which plays a crucial role in determining the overall system performance. Since the LNA is directly connected to the antenna, its noise characteristics significantly influence the quality of the received signal. Moreover, the signals captured by the antenna are typically weak, so the LNA must provide sufficient gain to amplify the signal effectively and pass it on to the next stage without distortion.
This paper presents a low noise amplifier designed for the 2.4 GHz band using the SM IC 0.13μm RF CMOS process. In wireless sensor network nodes, power consumption is a critical design constraint. Therefore, the amplifier must achieve a balance between low noise, high gain, and acceptable bandwidth, while maintaining good linearity and stability. However, optimizing for both minimum noise figure and maximum gain is not feasible. Thus, the challenge lies in achieving optimal input and output matching while keeping power consumption within limits, which is a major focus in the design of such amplifiers.
**1 Low Noise Amplifier Design**
**1.1 Circuit Structure**
The circuit architecture of the low noise amplifier used in this study is illustrated in Figure 1. The main structure employs a cascode differential configuration, which helps reduce the Miller effect and improves reverse isolation by lowering the input impedance. This configuration also enhances the stability of the amplifier by mitigating the impact of gate-drain capacitance and subsequent stages.
In this design, on-chip resistors R1 and R2 generate a bias voltage Vbias, which is applied to the gates of the common-source transistors M1 and M2 via Rg1 and Rg2. To minimize noise from the biasing resistors, Rg1 and Rg2 should have high resistance values. The common-gate transistors M3 and M4 further contribute to the stability and noise performance.
On-chip source inductors Ls1 and Ls2, along with gate-source capacitors Cex1 and Cex2, are matched with gate-strip inductors Lg1 and Lg2 to ensure proper input matching. Similarly, the output matching is achieved through inductors Ld1 and Ld2, which are connected in parallel with capacitors Cd1 and Cd2, and then in series with Cd3 and Cd4.
A half-circuit analysis of the differential cascode amplifier reveals key parameters. For MOS transistors operating in saturation, their transconductance and drain current are determined by gate width and bias conditions. The design uses a 1.2V supply voltage, with a gate-source voltage of 600 mV to ensure sufficient linearity and avoid cutoff.
To meet the power consumption requirement of 8 mW, the gate widths W1 and W3 of the common-source and common-gate transistors are adjusted. Simulations show that the working current is approximately 3 mA per half-circuit, totaling around 6 mA, which meets the design specifications.
The gain control circuit utilizes a signal addition approach, where gain control MOSFETs Mc1, Mc2, Mc3, and Mc4 are controlled by VC1 and VC2. By switching these transistors, the current through M3 can be adjusted, thereby changing its transconductance and ultimately the gain of the amplifier.
**1.2 Input Matching**
Figure 2 shows the input half-circuit of the low noise amplifier and its small-signal equivalent model. When the input terminals are not connected to additional capacitors Cex1 and Cex2, the input impedance is analyzed using the small-signal model. This analysis helps optimize the matching network for maximum signal transfer and minimal reflection.
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